做视频网站的公司有哪些,网站建设与管理专业课程,网站 参数,logo设计免费在线制作名称#xff1a;基于FPGA的DDS波形发生器VHDL代码Quartus仿真#xff08;文末获取#xff09;
软件#xff1a;Quartus
语言#xff1a;VHDL
代码功能#xff1a;
DDS波形发生器VHDL
1、可以输出正弦波、方波、三角波
2、可以控制输出波形的频率 DDS波形发生器原理…名称基于FPGA的DDS波形发生器VHDL代码Quartus仿真文末获取
软件Quartus
语言VHDL
代码功能
DDS波形发生器VHDL
1、可以输出正弦波、方波、三角波
2、可以控制输出波形的频率 DDS波形发生器原理 1. 工程文件 2. 程序文件 ROM IP核 3. 程序编译 4. RTL图 5. Testbench 6. 仿真图
整体仿真图 相位累加器模块 波形选择模块 正弦波ROM 三角波ROM 方波ROM 部分代码展示: LIBRARY ieee;USE ieee.std_logic_1164.all;
--信号发生器
ENTITY DDS_top ISPORT (clk_50M : IN STD_LOGIC;wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);--01输出sin10输出方波11输出三角波frequency : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--频率控制字控制输出波形频率值越大频率越大wave : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--输出波形);
END DDS_top;
ARCHITECTURE behave OF DDS_top IS
--例化模块COMPONENT wave_sel ISPORT (clk_50M : IN STD_LOGIC;wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);douta_fangbo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);douta_sanjiao : IN STD_LOGIC_VECTOR(7 DOWNTO 0);douta_sin : IN STD_LOGIC_VECTOR(7 DOWNTO 0);wave : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END COMPONENT;COMPONENT Frequency_ctrl ISPORT (clk_50M : IN STD_LOGIC;frequency : IN STD_LOGIC_VECTOR(7 DOWNTO 0);addra : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));END COMPONENT;
COMPONENT sin_ROM IS
PORT
(
address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock: IN STD_LOGIC : 1;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT fangbo_ROM IS
PORT
(
address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock: IN STD_LOGIC : 1;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT sanjiao_ROM IS
PORT
(
address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock: IN STD_LOGIC : 1;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;SIGNAL addra : STD_LOGIC_VECTOR(9 DOWNTO 0);SIGNAL douta_fangbo : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL douta_sanjiao : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL douta_sin : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN--方波ROMi_fangbo_ROM : fangbo_ROMPORT MAP (clock clk_50M,address addra,q douta_fangbo);--三角波ROMi_sanjiao_ROM : sanjiao_ROMPORT MAP (clock clk_50M,address addra,q douta_sanjiao);--sin波ROMi_sin_ROM : sin_ROMPORT MAP (clock clk_50M,address addra,q douta_sin);--相位累加器i_Frequency_ctrl : Frequency_ctrlPORT MAP (clk_50M clk_50M,frequency frequency,--频率控制字addra addra--输出地址);--波形选择控制i_wave_sel : wave_selPORT MAP (clk_50M clk_50M,wave_select wave_select,--01输出sin10输出方波11输出三角波douta_fangbo douta_fangbo,--方波douta_sanjiao douta_sanjiao,--三角douta_sin douta_sin,--正弦wave wave--输出波形 );END behave;源代码 扫描文章末尾的公众号二维码
