网站开发包括几部分,现代风格装修效果图,都江堰网站建设培训,微网站怎么用【RISC-V设计-05】- RISC-V处理器设计K0A之GPR 文章目录 【RISC-V设计-05】- RISC-V处理器设计K0A之GPR1.简介2.设计顶层3.内部结构4.端口说明5.设计代码6.总结 1.简介
通用寄存器#xff08;General Purpose Register#xff09;是处理器设计中的重要组成部分#xff0c;在…【RISC-V设计-05】- RISC-V处理器设计K0A之GPR 文章目录 【RISC-V设计-05】- RISC-V处理器设计K0A之GPR1.简介2.设计顶层3.内部结构4.端口说明5.设计代码6.总结 1.简介
通用寄存器General Purpose Register是处理器设计中的重要组成部分在数据处理和指令执行过程中发挥着关键作用对于计算机系统的整体性能和效率有着至关重要的影响。通用寄存器用于传送和暂存数据也可参与算术逻辑运算并保存运算结果。本模块内含有15个32bit的寄存器一个写操作端口两个读操作端口读写可同时操作。
2.设计顶层 3.内部结构 4.端口说明
序号端口方向位宽说明1core_clkinput1内核时钟2idu2gpr_weinput1通用寄存器组写使能高有效3idu2gpr_waddrinput4通用寄存器组写地址4idu2gpr_wdatainput32通用寄存器组写数据5idu2gpr_raddr1input4通用寄存器组读地址16gpr2idu_rdata1output32通用寄存器组读数据17idu2gpr_raddr2input4通用寄存器组读地址28gpr2idu_rdata2output32通用寄存器组读数据2
5.设计代码
// -------------------------------------------------------------------------------------------------
// Copyright 2024 Kearn Chen, kearn.chenaliyun.com
//
// Licensed under the Apache License, Version 2.0 (the License);
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an AS IS BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// -------------------------------------------------------------------------------------------------
// Description :
// 1. General Purpose Register, 32bit * 15 480bit
// -------------------------------------------------------------------------------------------------module k0a_core_gpr (input core_clk ,input idu2gpr_we ,input [3:0] idu2gpr_waddr ,input [31:0] idu2gpr_wdata ,input [3:0] idu2gpr_raddr1 ,output [31:0] gpr2idu_rdata1 ,input [3:0] idu2gpr_raddr2 ,output [31:0] gpr2idu_rdata2
);reg [31:0] x1_ra;
reg [31:0] x2_sp;
reg [31:0] x3_gp;
reg [31:0] x4_tp;
reg [31:0] x5_t0;
reg [31:0] x6_t1;
reg [31:0] x7_t2;
reg [31:0] x8_s0;
reg [31:0] x9_s1;
reg [31:0] xa_a0;
reg [31:0] xb_a1;
reg [31:0] xc_a2;
reg [31:0] xd_a3;
reg [31:0] xe_a4;
reg [31:0] xf_a5;wire x1_rd1 (idu2gpr_raddr1 4h1);
wire x2_rd1 (idu2gpr_raddr1 4h2);
wire x3_rd1 (idu2gpr_raddr1 4h3);
wire x4_rd1 (idu2gpr_raddr1 4h4);
wire x5_rd1 (idu2gpr_raddr1 4h5);
wire x6_rd1 (idu2gpr_raddr1 4h6);
wire x7_rd1 (idu2gpr_raddr1 4h7);
wire x8_rd1 (idu2gpr_raddr1 4h8);
wire x9_rd1 (idu2gpr_raddr1 4h9);
wire xa_rd1 (idu2gpr_raddr1 4ha);
wire xb_rd1 (idu2gpr_raddr1 4hb);
wire xc_rd1 (idu2gpr_raddr1 4hc);
wire xd_rd1 (idu2gpr_raddr1 4hd);
wire xe_rd1 (idu2gpr_raddr1 4he);
wire xf_rd1 (idu2gpr_raddr1 4hf);wire x1_rd2 (idu2gpr_raddr2 4h1);
wire x2_rd2 (idu2gpr_raddr2 4h2);
wire x3_rd2 (idu2gpr_raddr2 4h3);
wire x4_rd2 (idu2gpr_raddr2 4h4);
wire x5_rd2 (idu2gpr_raddr2 4h5);
wire x6_rd2 (idu2gpr_raddr2 4h6);
wire x7_rd2 (idu2gpr_raddr2 4h7);
wire x8_rd2 (idu2gpr_raddr2 4h8);
wire x9_rd2 (idu2gpr_raddr2 4h9);
wire xa_rd2 (idu2gpr_raddr2 4ha);
wire xb_rd2 (idu2gpr_raddr2 4hb);
wire xc_rd2 (idu2gpr_raddr2 4hc);
wire xd_rd2 (idu2gpr_raddr2 4hd);
wire xe_rd2 (idu2gpr_raddr2 4he);
wire xf_rd2 (idu2gpr_raddr2 4hf);wire x1_wr (idu2gpr_waddr 4h1) idu2gpr_we;
wire x2_wr (idu2gpr_waddr 4h2) idu2gpr_we;
wire x3_wr (idu2gpr_waddr 4h3) idu2gpr_we;
wire x4_wr (idu2gpr_waddr 4h4) idu2gpr_we;
wire x5_wr (idu2gpr_waddr 4h5) idu2gpr_we;
wire x6_wr (idu2gpr_waddr 4h6) idu2gpr_we;
wire x7_wr (idu2gpr_waddr 4h7) idu2gpr_we;
wire x8_wr (idu2gpr_waddr 4h8) idu2gpr_we;
wire x9_wr (idu2gpr_waddr 4h9) idu2gpr_we;
wire xa_wr (idu2gpr_waddr 4ha) idu2gpr_we;
wire xb_wr (idu2gpr_waddr 4hb) idu2gpr_we;
wire xc_wr (idu2gpr_waddr 4hc) idu2gpr_we;
wire xd_wr (idu2gpr_waddr 4hd) idu2gpr_we;
wire xe_wr (idu2gpr_waddr 4he) idu2gpr_we;
wire xf_wr (idu2gpr_waddr 4hf) idu2gpr_we;assign gpr2idu_rdata1 ({32{x1_rd1}} x1_ra) | ({32{x2_rd1}} x2_sp) |({32{x3_rd1}} x3_gp) | ({32{x4_rd1}} x4_tp) |({32{x5_rd1}} x5_t0) | ({32{x6_rd1}} x6_t1) |({32{x7_rd1}} x7_t2) | ({32{x8_rd1}} x8_s0) |({32{x9_rd1}} x9_s1) | ({32{xa_rd1}} xa_a0) |({32{xb_rd1}} xb_a1) | ({32{xc_rd1}} xc_a2) |({32{xd_rd1}} xd_a3) | ({32{xe_rd1}} xe_a4) |({32{xf_rd1}} xf_a5) ;assign gpr2idu_rdata2 ({32{x1_rd2}} x1_ra) | ({32{x2_rd2}} x2_sp) |({32{x3_rd2}} x3_gp) | ({32{x4_rd2}} x4_tp) |({32{x5_rd2}} x5_t0) | ({32{x6_rd2}} x6_t1) |({32{x7_rd2}} x7_t2) | ({32{x8_rd2}} x8_s0) |({32{x9_rd2}} x9_s1) | ({32{xa_rd2}} xa_a0) |({32{xb_rd2}} xb_a1) | ({32{xc_rd2}} xc_a2) |({32{xd_rd2}} xd_a3) | ({32{xe_rd2}} xe_a4) |({32{xf_rd2}} xf_a5) ;always (posedge core_clk) if(x1_wr) x1_ra idu2gpr_wdata;
always (posedge core_clk) if(x2_wr) x2_sp idu2gpr_wdata;
always (posedge core_clk) if(x3_wr) x3_gp idu2gpr_wdata;
always (posedge core_clk) if(x4_wr) x4_tp idu2gpr_wdata;
always (posedge core_clk) if(x5_wr) x5_t0 idu2gpr_wdata;
always (posedge core_clk) if(x6_wr) x6_t1 idu2gpr_wdata;
always (posedge core_clk) if(x7_wr) x7_t2 idu2gpr_wdata;
always (posedge core_clk) if(x8_wr) x8_s0 idu2gpr_wdata;
always (posedge core_clk) if(x9_wr) x9_s1 idu2gpr_wdata;
always (posedge core_clk) if(xa_wr) xa_a0 idu2gpr_wdata;
always (posedge core_clk) if(xb_wr) xb_a1 idu2gpr_wdata;
always (posedge core_clk) if(xc_wr) xc_a2 idu2gpr_wdata;
always (posedge core_clk) if(xd_wr) xd_a3 idu2gpr_wdata;
always (posedge core_clk) if(xe_wr) xe_a4 idu2gpr_wdata;
always (posedge core_clk) if(xf_wr) xf_a5 idu2gpr_wdata;endmodule6.总结
本文实现了一个基本的通用寄存器组支持一写双读操作。对于一写双读操作这可以显著提高数据处理的并行性在诸如流水线处理等场景中能够提高系统的性能。比如在一个 CPU 的指令执行阶段可能同时需要读取两个寄存器的值进行运算而新的数据又可以在同一周期被写入另一个寄存器。
每个寄存器都是32位宽包含0地址寄存器总共有16个的寄存器。设计中的寄存器全部采用无复为寄存器优化时序减少面积。无复位寄存器的选择可能会简化电路结构但也需要在系统初始化和异常处理时特别注意数据的初始状态和稳定性。例如在系统启动时需要通过软件初始化来确保寄存器中的值是合理的起始值。事实上软件也不应该依赖于寄存器的默认值。
在综合时工具会为15个寄存器插入时钟门控Clocke Gating Cell以降低动态功耗。由于汇编代码中使用的为ABI名称所以寄存器命名带有ABI名称方便调试和查看。通过逐一对每个寄存器编写逻辑代码避免了对X0寄存器的译码减少综合后电路面积。
