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FPGA没有双边缘触发触发器，@（posedge clk或negedge clk）会报错

“FPGA（以及其他任何地方）上的触发器是一个具有一个时钟且仅对该时钟的一个边缘敏感的器件。”参考verilog为什么不能双边沿触发

实现双边沿的两种方法

module top_module (input clk,input d,output q
);reg a,b;always@(posedge clk)begina <= d;endalways@(negedge clk)beginb <= d;endassign q = clk?a:b;endmodule

HDLbits官方答案 

module top_module(input clk,input d,output q);reg p, n;// A positive-edge triggered flip-flopalways @(posedge clk)p <= d ^ n;// A negative-edge triggered flip-flopalways @(negedge clk)n <= d ^ p;// Why does this work? // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.// After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.// At each (positive or negative) clock edge, p and n FFs alternately// load a value that will cancel out the other and cause the new value of d to remain.assign q = p ^ n;// Can't synthesize this./*always @(posedge clk, negedge clk) beginq <= d;end*/endmodule