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块RAM读/写同步模式
您可以配置块RAM资源#xff0c;为提供以下同步模式给定的读/写端口#xff1a;
•先读取#xff1a;在加载新内容之前先读取旧内容。
•先写#xff1a;新内容立即可供阅读先写也是众所周知的如通读。
•无变化为提供以下同步模式给定的读/写端口
•先读取在加载新内容之前先读取旧内容。
•先写新内容立即可供阅读先写也是众所周知的如通读。
•无变化数据输出不会随着新内容加载到RAM而变化。
Vivado合成为所有这些同步模式提供了推理支持。你可以描述了用于RAM的每个端口的不同同步模式。
分布式RAM示例
以下部分提供了分布式RAM的VHDL和Verilog编码示例。
具有异步读取编码的双端口RAM Verilog示例 Filename: rams_dist.v // Dual-Port RAM with Asynchronous Read (Distributed RAM) // File: rams_dist.v module rams_dist (clk, we, a, dpra, di, spo, dpo); input clk; input we; input [5:0] a; input [5:0] dpra; input [15:0] di; output [15:0] spo; output [15:0] dpo; reg [15:0] ram [63:0]; always (posedge clk) begin if (we) ram[a] di; end assign spo ram[a]; assign dpo ram[dpra]; endmodule Single-Port RAM with Asynchronous Read Coding Example (VHDL) Filename: rams_dist.vhd -- Single-Port RAM with Asynchronous Read (Distributed RAM) -- File: rams_dist.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rams_dist is port( clk : in std_logic; we : in std_logic; a : in std_logic_vector(5 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0) ); end rams_dist; architecture syn of rams_dist is type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0); signal RAM : ram_type; begin process(clk) begin if (clkevent and clk 1) then if (we 1) then RAM(to_integer(unsigned(a))) di; end if; end if; end process; do RAM(to_integer(unsigned(a))); end syn; 单端口块RAM 以下部分提供了单端口块RAM的VHDL和Verilog编码示例。 带可重置数据输出的单端口块RAMVerilog Filename: rams_sp_rf_rst.v // Block RAM with Resettable Data Output // File: rams_sp_rf_rst.v module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout); input clk; input en; input we; input rst; input [9:0] addr; input [15:0] di; output [15:0] dout; reg [15:0] ram [1023:0]; reg [15:0] dout; always (posedge clk) begin if (en) //optional enable begin if (we) //write enable ram[addr] di; if (rst) //optional reset dout 0; else dout ram[addr]; end end endmodule Single Port Block RAM with Resettable Data Output (VHDL) Filename: rams_sp_rf_rst.vhd -- Block RAM with Resettable Data Output -- File: rams_sp_rf_rst.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rams_sp_rf_rst is port( clk : in std_logic; en : in std_logic; we : in std_logic; rst : in std_logic; addr : in std_logic_vector(9 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0) ); end rams_sp_rf_rst; architecture syn of rams_sp_rf_rst is type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; begin process(clk) begin if clkevent and clk 1 then if en 1 then -- optional enable if we 1 then -- write enable ram(to_integer(unsigned(addr))) di; end if; if rst 1 then -- optional reset do (others 0); else do ram(to_integer(unsigned(addr))); end if; end if; end if; end process; end syn; Single-Port Block RAM Write-First Mode (Verilog) Filename: rams_sp_wf.v // Single-Port Block RAM Write-First Mode (recommended template) // File: rams_sp_wf.v module rams_sp_wf (clk, we, en, addr, di, dout); input clk; input we; input en; input [9:0] addr; input [15:0] di; output [15:0] dout; reg [15:0] RAM [1023:0]; reg [15:0] dout; always (posedge clk) begin if (en) begin if (we) begin RAM[addr] di; dout di; end else dout RAM[addr]; end end endmodule Single-Port Block RAM Write-First Mode (VHDL) Filename: rams_sp_wf.vhd -- Single-Port Block RAM Write-First Mode (recommended template) -- -- File: rams_sp_wf.vhd -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rams_sp_wf is port( clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(9 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0) ); end rams_sp_wf; architecture syn of rams_sp_wf is type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0); signal RAM : ram_type; begin process(clk) begin if clkevent and clk 1 then if en 1 then if we 1 then RAM(to_integer(unsigned(addr))) di; do di; else do RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end syn; Single-Port RAM with Read First (VHDL) Filename: rams_sp_rf.vhd -- Single-Port Block RAM Read-First Mode -- rams_sp_rf.vhd -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rams_sp_rf is port( clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(9 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0) ); end rams_sp_rf; architecture syn of rams_sp_rf is type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0); signal RAM : ram_type; begin process(clk) begin if clkevent and clk 1 then if en 1 then if we 1 then RAM(to_integer(unsigned(addr))) di; end if; do RAM(to_integer(unsigned(addr))); end if; end if; end process; end syn; Single-Port Block RAM No-Change Mode (Verilog) Filename: rams_sp_nc.v // Single-Port Block RAM No-Change Mode // File: rams_sp_nc.v module rams_sp_nc (clk, we, en, addr, di, dout); input clk; input we; input en; input [9:0] addr; input [15:0] di; output [15:0] dout; reg [15:0] RAM [1023:0]; reg [15:0] dout; always (posedge clk) begin if (en) begin if (we) RAM[addr] di; else dout RAM[addr]; end end endmodule Single-Port Block RAM No-Change Mode (VHDL) Filename: rams_sp_nc.vhd -- Single-Port Block RAM No-Change Mode -- File: rams_sp_nc.vhd -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rams_sp_nc is port( clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(9 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0) ); end rams_sp_nc; architecture syn of rams_sp_nc is type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0); signal RAM : ram_type; begin process(clk) begin if clkevent and clk 1 then if en 1 then if we 1 then RAM(to_integer(unsigned(addr))) di; else do RAM(to_integer(unsigned(addr))); end if; end if; end if; end process; end syn;
